1. Field of the Invention
The present invention relates to an oscillation circuit and in particular to an oscillation circuit incorporated in an integrated circuit that generates signals at a specific frequency, such as, for example, a clock signal.
2. Description of the Related Art
With the rapid increase in miniaturized portable electronic devices, a need exists for semiconductors for these devices that operate with lower power consumption rates, and specifically, at lower voltage supply levels. Similarly, the oscillation circuitry incorporated into such semiconductor integrated circuits should operate with stable frequency characteristics with the lower supply voltages and the lower power consumption rates designed for today's semiconductors.
FIG. 1 shows a first example of conventional oscillation circuits. A first inverter 1a receives an oscillation output signal Vout from an output terminal T.sub.0. The inverter 1a is a hysteresis inverter circuit which has the hysteresis characteristic that different inversion threshold values exist depending on whether the voltage level of the input signal rises or whether the voltage level falls. Hereinafter, the threshold value for the former case is called a rising or high threshold value V.sub.IH and the threshold value for the latter case is called a falling or low threshold value V.sub.IL.
The output signal, SG1, of the first inverter 1a is input to a second inverter 1b. This oscillation circuit includes a NOR gate 2a which has first and second input terminals. The first input terminal of the NOR gate 2a receives the output signal, SG2, of the second inverter 1b. The output signal, SG3, of the NOR gate 2a is supplied as an input signal SG4 via a capacitor C1 to the input terminal of a third inverter circuit 1c. A supply voltage V.sub.CC is supplied via a resistor R1 to the input terminal of the inverter 1c. The resistor R1 and the capacitor C1 form a differentiator, i.e., a circuit whose output voltage is proportional to the rate of change of the input voltage.
The output signal, SG5, of the third inverter 1c is input to the second input terminal of the NOR gate 2a and to the input terminal of a fourth inverter 1d. The output signal, SG6, of the inverter 1d is input to the first input terminal of a NAND gate 3a. A signal ST instructing the start of oscillation is input to the second input terminal of the NAND gate 3a. The output signal, SG7, of the NAND gate 3a is input to the gates of a P channel MOS transistor Tr1 and an N channel MOS transistor Tr2. The transistor Tr1 has a source connected to a power supply V.sub.CC and a drain connected via a resistor R2 to the output terminal T.sub.0. The transistor Tr2 has a drain connected to the output terminal T.sub.0 and a source connected to the ground GND. The output terminal T.sub.0 is connected via a capacitor C2 to the ground GND.
The operation of the oscillation circuit will now be described with reference to FIG. 2. With this oscillation circuit supplied with the power from the power supply V.sub.CC and with a low level oscillation start signal ST, the output signal SG7 of the NAND gate 3a goes high. This turns on the transistor Tr2, causing the oscillation output signal Vout to go low. At this time, the input signal SG4 of the third inverter 1c is high and the output signal SG5 of the inverter circuit 1c is low. Since the output signal SG2 of the second inverter 1b is low, the output signal SG3 of the NOR gate 2a is high, as are both terminals ends of the capacitor C1. Under this situation, when the oscillation start signal ST goes high, the output signal SG7 of the NAND gate 3a goes low, turning off the transistor Tr2 and turning on the transistor Tr1. Consequently, the capacitor C2 is charged via the resistor R2, causing the potential of the oscillation output signal Vout to rise from the ground level in accordance with the time constant which is determined by the resistor R2 and the capacitor C2, as shown in FIG. 2.
When the potential of the oscillation output signal Vout reaches the high threshold value V.sub.IH for the first inverter 1a, the output signal SG1 of the inverter 1a goes low causing the output signal SG2 of the second inverter 1b to go. As a result, the output signal SG3 of the NOR gate 2a goes low, as does the input signal SG4 of the third inverter 1c. When the level of the input signal SG4 of the inverter 1c is lower than the threshold value V.sub.IH for the inverter 1c, the output signal SG5 of the inverter 1c is maintained. Consequently, the output signal SG6 of the fourth inverter 1d goes low and the output signal SG7 of the NAND gate 3a goes high. This turns off the transistor Tr1 and turns on the transistor Tr2, so that the charges accumulated in the capacitor C2 are discharged to the ground GND via the transistor Tr2. This decreases the potential of the oscillation output signal Vout. When the output signal SG3 of the NOR gate 2a goes low, the charge current is supplied via the resistor R1 to the capacitor C1 from the power supply V.sub.CC, causing the potential of the input signal SG4 of the third inverter 1c to rise in accordance with the time constant determined by the capacitor C1 and the resistor R1.
When the potential of the input signal SG4 rises above the threshold value V.sub.IH for the third inverter 1c, the output signal SG5 of the inverter circuit 1c is inverted to a low level. As a result, the output signal SG6 of the fourth inverter 1d goes high and the output signal SG7 of the NAND gate 3a goes low. This turns off the transistor Tr2 and turns on the transistor Tr1, so that the potential of the oscillation output signal Vout, which has dropped nearly to the ground level, starts rising again. When the potential of the oscillation output signal Vout falls down to the low threshold value V.sub.IL, the output signal SG1 of the inverter 1a goes high, causing the output signal SG2 of the second inverter 1b to go low. The output signal SG3 of the NOR gate 2a is, however, kept high as long as the output signal SG5 of the third inverter 1c is high.
The duration when the transistor Tr2 is turned on is determined by the differential circuit formed by the resistor R1 and the capacitor C1. The time constant of the differential circuit is set in such a manner that the transistor Tr2 is kept on even if the potential of the oscillation output signal Vout falls below the low threshold value V.sub.IL for the first inverter 1a, and that the potential of the oscillation output signal Vout starts rising when the oscillation output signal Vout falls nearly to the ground level. In the above-described manner, the conventional oscillation circuit produces oscillation signals at the oscillation frequency in accordance with the time constants defined by the values of the resistor combinations R1,C1 and R2,C2.
In order to permit the conventional oscillation circuit to start its oscillation, the supply voltage V.sub.CC should be supplied to the oscillation circuit. In addition, a high level oscillation start signal ST, should be supplied to the NAND gate 3a. This requires a separate circuit to supply the oscillation circuit with the oscillation start signal ST.
When the supply voltage V.sub.CC falls due to some reason, the load driving performance of the NOR gate 2a is reduced. Even when the NOR gate 2a outputs a low level output signal SG3, the input signal SG4 of the third inverter 1c will not drop to ground. This decreases the duration of time from when the NOR gate 2a outputs the low level output signal SG3 to the time when the input signal SG4 of the third inverter 1c exceeds the threshold value for the inverter 1c (i.e., the pulse width of the H-level output signal SG5 from the inverter 1c). This, in turn, shortens the duration of time during which the transistor Tr2 is turned on, preventing the charge accumulated in the capacitor C2 from being adequately discharged. When the oscillation output signal Vout fails to drop to ground, the voltage swing of the oscillation output signal Vout is reduced. If decreases in the supply voltage V.sub.CC further shortens the ON duration during which the transistor Tr2 is turned on, the potential of the oscillation output signal Vout cannot fall below the low threshold value V.sub.IL for the first inverter 1a. In this case, no oscillation occurs even when the oscillation start signal ST is supplied to the oscillation circuit.
FIG. 3 shows the relationship between the supply voltage V.sub.CC and the rate of a change in the frequency of the oscillation output signal Vout in the oscillation circuit shown in FIG. 1. Here, for example, the resistance R2 is set to 135 kO and the capacitance C2 is set to 815 pF. The choice of these values cause the frequency of the oscillation output signal Vout to be 8 kHz when the supply voltage V.sub.CC is 1.5 V. The rate of the frequency change R (%) is computed from the following equation. EQU R=100.times.(f.sub.1.5 V -f.sub.VCC)/f.sub.1.5 V
where f.sub.1.5 V is the frequency of the output signal Vout when the supply voltage V.sub.CC =1.5 V, and f.sub.VCC is the frequency of the output signal Vout with respect to the supply voltage V.sub.CC.
In this oscillation circuit, when the supply voltage V.sub.CC is lower than 1.4 V, signal oscillation will not occur. The resistance of the resistor R1 and the capacitance of capacitor C1 need to be set large enough to ensure that the potential of output signal Vout, at a high threshold V.sub.IH, has adequate time to decrease in potential to ground or zero potential. In other words, the time constant controlled by resistor R1 and capacitor C1 needs to be carefully set. These values, moreover, need to be set large enough to ensure the complete discharge of capacitor C2, even with a reduced load driving performance of the NOR gate 2a.
However, increasing the capacitance of the capacitor C1 and the resistance of the resistor R1 formed on a semiconductor substrate increases the areas they occupy on the substrate. This reduces the integration level of semiconductor circuits. If the voltage swing of the oscillation output signal Vout is reduced, the oscillation frequency output signal Vout will be significantly affected by variations in the high threshold value V.sub.IH and low threshold value V.sub.IL of the first inverter 1a. This often occurs due to variations in quality in the manufacturing process. In addition, the reduction in the voltage swing of the oscillation output signal Vout causes the frequency of the output signal Vout to be influenced by the operational delay time of the inverter 1a.
Undesirable variations in oscillation frequency of signal Vout, due to the delay time of inverter 1a, may be diminished by increasing the ratio of each transistors' gate width to their gate length to shorten the delay time of inverter 1a. Increasing the gate width/length ratio of the transistors in inverter 1a, however, results in an increase in the flowthrough currents in the inverter 1a and thus in an increase in the oscillating circuits power consumption. In addition, the rising speed of the oscillating signal Vout input to the inverter 1a is undesirably slow, as shown in FIG. 2.
FIG. 4 shows a second conventional oscillation circuit. This oscillation circuit has odd-numbered stages of inverters 1e, 1f and 1g connected in series (three stages inverters in this case). The output terminal of the third inverter 1g is connected to the input terminal of the first inverter 1e so that the inverter 1e to 1g and a resistor R3 form a closed loop circuit. The input terminal of the first inverter 1e, which is a hysteresis inverter, is connected to the ground GND via a capacitor C3. In this oscillation circuit, the output signal of the third inverter 1g is delayed in accordance with the time constant of an integration circuit formed by the resistor R3 and the capacitor C3. The delayed signal is input to the hysteresis inverter 1e and the charged potential of the capacitor C3 is determined by the inverter 1e. Accordingly, the output signal Vout oscillates at the oscillation frequency according to the time constant, and the voltage swing of the output signal Vout is established as the voltage difference between the high threshold value V.sub.IH and low threshold value V.sub.IL of the inverter 1e.
According to the second oscillation circuit, the voltage swing of the output signal Vout is smaller than the voltage swing in the first conventional oscillation circuit. In order to accurately set the frequency of the oscillation signal Vout, the high threshold value V.sub.IH and low threshold value V.sub.IL for the first inverter 1e should be set accurately. The threshold values V.sub.IH and V.sub.IL vary due to variations in quality during the manufacturing process of oscillation circuits. It is therefore difficult to accurately set the frequency of the oscillation signal Vout for this second type of oscillation circuit.
FIG. 5 shows the relationship between the supply voltage V.sub.CC and the rate of frequency change, R, of the oscillation output signal Vout in the oscillation circuit shown in FIG. 4. Here, for example, the resistance R3 is set to 135 kO and the capacitance C3 is set to 2212 pF. This setting permits the frequency of the oscillation signal Vout to be 8 kHz when the supply voltage V.sub.CC is 1.5 Volt. The graph in FIG. 5 indicates that the oscillation frequency greatly varies as the supply voltage V.sub.CC changes.
FIG. 6 shows a third conventional oscillation circuit. This oscillation circuit has odd-numbered stages of inverters 1h, 1i and 1j connected in series (three stages inverters in this case). The output terminal of the third inverter 1j is connected via a resistor R4 to the input terminal of the first inverter 1h, so that the inverters 1h to 1j and the resistor R4 form a closed loop circuit. The output terminal of the second inverter 1i is connected via a capacitor C4 to the input terminal of the first inverter 1h. This oscillation circuit generates an oscillation signal in accordance with the time constant of the circuit comprising the resistor R4 and the capacitor C4.
In this circuit, when the output signal of the second inverter 1i goes low, the input signal potential of the first inverter 1h falls below ground. When the output signal of the second inverter 1i goes high, the input signal potential of the first inverter 1h rises above the level of the supply voltage V.sub.CC. In order to protect the first inverter 1h against those very high and low input potentials, a protection diode should be connected to the input terminal of the inverter 1h. If the protection diode is connected to the input terminal of the inverter 1h, however, this diode may absorbs the charges accumulated in the capacitor C4 and may influence the time constant determined by the capacitor C4 and the resistor R4. It is therefore very difficult to control the frequency of the oscillation signal based on the time constant determined by the capacitor C4 and resistor R4.